SYSTEM VERILOG FOR VERIFICATION

Dive into SystemVerilog for Verification with us & learn the language’s nuances and applications to enhance your skills in VLSI verification.

Why Choose a System Verilog For Verification?

This course offers hands on experience with various verification methodologies such as Constraint Random Coverage Driven Verification (CRCDV), using the languages like SystemVerilog on the project life cycle from Verification planning to Verification signoff, making the trainees industry ready.

Prerequisite: Verilog Concepts
Learning Mode: Blended (Pre-Recorded + Live Q & A)
Course Duration: 2 Months
EDA Tool : Siemens – Questasim
Course Fees: Rs.25,000/- ( Inc. GST)

Key Highlights

  • Industry-Standard Curriculum
  • Blended course with Support Material, Labs, and Projects
  • Course Delivered by Industry Experts
  • Live Q&A and Review Sessions
  • Mobile Apps – Attend Anywhere Anytime
  • Certificate on successful completion of the course
  • 24*7 VPN Access

Programme Modules

  • Advance Verilog
  • Verification Methodology overview
  • Various Language concepts – Datatypes,
  • Memories, Interface & clocking block, Randomization.
  • OOP Concepts – Basic & Advanced
  • TB Components – V-Plan, TB Architecture
  • Functional Coverage
  • Pilot Project

For detailed Curriculum

Click to Download